1. Field of the Invention
The present invention relates to a voltage multiplier circuit and a nonvolatile semiconductor memory device having the voltage multiplier circuit, and particularly to improvement of a voltage multiplier formed in a semiconductor integrated circuit device such as an EEPROM.
2. Description of the Related Art
Conventionally, in a semiconductor nonvolatile semiconductor memory device (EEPROM), since a voltage, which is higher than a power supply voltage, is needed at the time of writing and erasing a signal, there is used a voltage multiplier to which a plurality of multiplier cells CL are connected in series as shown in FIG. 1. The multiplier cell CL comprises a capacitor C and a switching element Q as shown in FIG. 2A and FIG. 2B. The specific structure of the voltage multiplier circuit is shown in FIG. 3A, and clocks .phi., /.phi. for driving the circuit are shown in FIG. 3B.
In the voltage multiplier circuit, the number of multiplier cells to be connected in series for an output is determined in accordance with the value of high voltage as required, and the voltage multiplier circuit is generally driven with the unchanged number of the multiplier cells. Therefore, in the conventional voltage multiplier circuit, charge transfer efficiency is unnecessarily dropped for a period of time when the smaller number of the multiplier cells connected in series is sufficient for multiplier voltage start up. Due to this, there was a problem in that it took much time to obtain a necessary voltage.
As mentioned above, in the conventional voltage multiplier circuit formed in the semiconductor integrated circuit device such as EEPROM, etc, there was a problem in that charge transfer efficiency is unnecessarily dropped and a large amount of multiplier voltage rising time was required for a period of time when the required number of the multiplier cells to be connected in series may be smaller than the predetermined number of the multiplier cells.